Continued reduction in end product size of mobile electronic devices such as smart phones and ultrabooks is a driving force for the development of packaging with a small form factor having improved thermal management capabilities. In legacy substrate architectures, thermal management is handled both internal and external to the substrate structure. Solutions external to the substrate structure typically use an integrated heat sink that may be attached via a thermal paste to the logic die.
Solutions internal to the substrate structure typically involve increasing the overall thermal conductivity by, for example, using a special high thermal conductivity build up material, forming dedicated copper thermal vias, and/or reducing the core thickness. Examples may also include increasing the heat capacity using thicker copper traces and/or embedding copper blocks/chips. However, these legacy implementations have challenges of sacrificing design rule flexibility. For example, additional real estate on the substrate must be reserved to accommodate embedded copper chip and copper thermal vias; increasing copper trace thickness will limit line space scaling; and relying on an outsourced, proprietary build up material with high thermal conductivity may be costly.